View ICS9148-18_6311031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated circuit systems, inc. general description features ICS9148-18 block diagram pentium/pro tm system clock chip 9148-18 rev b 07/08/98 pin configuration 28 pin ssop pentium is a trademark on intel corporation. ? generates system clocks for cpu, pci, plus 14.314 mhz ref0. ? supports single or dual processor systems ? skew from cpu (earlier) to pci clock (rising edges for 100/33.3mhz) 1 to 4ns ? separate 2.5v and 3.3v supply pins ? 2.5v or 3.3v output: cpu ? 3.3v outputs: pci, ref ? no power supply sequence requirements ? uses external 14.318mhz crystal, no external load cap required for c l =18pf crystal ? 28 pin 209 mil ssop the ICS9148-18 is a clock synthesizer chip for pentium and pentiumpro cpu based desktop/notebook systems that will provide all necessary clock timing. features include two cpu and six pci clocks. one reference output is available equal to the crystal frequency. additionally, the device meets the pentium power-up stabilization requirement, acheiving stable cpu and pci clocks 2ms after power-up. pd# pin can enable a low power mode by stopping crystal osc and pll stages. other power management features include, cpu_stop# which stops cpu (0:1) clocks, and pci_stop# which stops pciclk (0:4) clocks. high drive cpuclk outputs typically provide greater than 1 v/ns slew rate into 20pf loads. pciclk outputs typically provide better than 1v/ns slew rate into 30pf loads while maintaining 505% duty cycle. the ref clock output typically provides better than 0.5v/ns slew rates. the ICS9148-18 accepts a 14.318mhz reference crystal or clock as its input and runs on a 3.3v core supply. ground groups gnd = ground source core gnd1 = ref0, x1, x2 gnd2 = pciclk_f, pciclk (0:4) gndl = cpuclk (0:1) power groups vdd = supply for pll core vdd1 = ref0, x1, x2 vdd2 = pciclk_f, pciclk (0:4) vddl = cpuclk (0:1) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ICS9148-18 pin descriptions select functions (functionality determined by fs0 and sel100/66# pin, see below) notes: 1. tclk is a test clock driven on the x1 (crystal in pin) input during test mode. pin number pin name type description 26 ref0 out 14.318mhz clock output 28 gnd1 pwr ground for ref outputs 1x1in xtal_in 14.318mhz crystal input, has internal 33pf load cap and feed back resistor from x2 2 x2 out xtal_out crystal output, has internal load cap 33pf 3, 12 gnd2 pwr ground for pci outputs 4 pciclk_f out free running pci output 5, 7, 8, 10, 11 pciclk (0:4) out pci clock outputs. ttl compatible 3.3v 6, 9 vdd2 pwr power for pciclk outputs, nominally 3.3v 13, 21 vdd pwr isolated power for core, nominally 3.3v 14, 20 gnd pwr isolated ground for core 15 sel100/66.6# in select pin for enabling 100mhz or 66.6mhz h=100mhz, l=66.6mhz (pci always synchronous 33.3mhz) 16 fs0 in frequency select pin 17 pd# in powers down chip, active low 18 cpu_stop# in halts cpu clocks at logic "0" level when low 19 pci_stop# in halts pci bus at logic "0" level when low 25 vddl pwr power for cpu outputs, nominally 2.5v 22 gndl pwr ground for cpu outputs. 23, 24 cpuclk (1:0) out cpu and host clock outputs @ 2.5v 27 vdd1 pwr power for ref outputs. functionality cpuclk pci, pci_f ref0 tristate hi - z hi - z hi - z testmode tclk/2 1 tclk/6 1 tclk 1 sel 100/66# fs0 function 00 tri-state 0 - (reserved) 0 - (reserved) 0 1 active 66.6mhz cpu, 33.3 pci 10 test mode 1 - (reserved) 1 - (reserved) 1 1 active 100mhz cpu, 33.3 pci
3 ICS9148-18 technical pin function descriptions vdd(1,2) this is the power supply to the internal core logic of the device as well as the clock output buffers for ref0, pciclk (0:4), and pciclk_f. this pin operates at 3.3v volts. clocks from the buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. vddl this is the power supply for the cpuclk output buffers. the voltage level for these outputs may be 2.5 or 3.3volts. clocks from the buffers that this pin supplies will have a voltage swing from ground to vddl. for the actual guaranteed high and low voltage levels of these clocks, please consult the dc parameter table in this data sheet. gnd(1,2) this is the power supply ground (common or negative) return pin for the internal core logic and all the pci output buffers. gndl this is the ground for cpuclk output buffers. x1 this input pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also has an internal crystal loading capacitor that is connected to ground. with a nominal value of 33pf, no external load cap is needed for a c l =17 to 18pf crystal. x2 this output pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the crystal. the x2 pin also has an internal loading capacitor, nominally 33pf. cpuclk (0:1) these output pins are the clock outputs that drive processor and other cpu related circuitry that requires clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by the voltage level applied to the vddl pin of the device. see the functionality table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. ref0 the ref output is fixed frequency clock that runs at the same frequency as the input reference clock or the crystal (typically 14.31818mhz) attached across x1 and x2. pciclk_f this output is equal to pciclk(0:4) and is free running, and will not be stopped by pci_stop#. pciclk (0:4) these output clocks generate all the pci timing requirements for a pentium/pro based system. they conform to the current pci specification. select 100/66.6mhz# this input pin controls the frequency of the clocks at the cpu & pciclk output pins. if a logic ?1? value is present on this pin, the 100mhz clock is selected. if a logic ?0? is used, the 66.6mhz frequency is selected. the pci clock is multiplexed to run at 33.3mhz for both select cases. pci is synchronous at the rising edge of pci to the cpu rising edge (with the skew making cpu early). pd# this is an asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and crystal are stopped. power down will also place all the outputs in a low state at the end of their current cycle. the latency of power down will not be greater than 3ms. cpu_stop# this is a synchronous active low input pin used to stop the cpuclk clocks in an active low state. all other clocks will continue to run while this function is enabled. the cpuclks will have a turn on latency of at least 3 cpu clocks. pci_stop# this is a synchronous active low input pin used to stop the pciclk clocks in an active low state. it will not effect pciclk_f nor any other outputs.
4 ICS9148-18 power management ICS9148-18 power management requirements clock enable configuration full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. during power up and power down operations using the pd# pin will not cause clocks of a short or longer pulse than that of the running clock . the first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry . board routing and signal loading may have a large impact on the initial clock distortion also. notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . 3. power up latency is when pd# goes inactive (high) to when the first valid clocks are output by the device. 4. power down has controlled clock counts applicable to cpuclk, pciclk only. the ref and ioapic will be stopped independant of these. signal signal state latency no. of rising edges of free running pciclk cpu_ stop# 0 (disabled) 2 1 1 (enabled) 1 1 pci_stop# 0 (disabled) 2 1 1 (enabled) 1 1 pd# 1 (normal operation) 3 3ms 0 (power down) 4 2max cpu_stop# pci_stop# pwr_dwn# cpuclk pciclk ref crystal vcos x x 0 low low stopped off off 0 0 1 low low running running running 0 1 1 low 33.3 mhz running running running 1 0 1 100/66.6mhz low running running running 1 1 1 100/66.6mhz 33.3 mhz running running running
5 ICS9148-18 pci_stop# timing diagram pci_stop# is an asynchronous input to the ICS9148-18 . it is used to turn off the pciclk (0:4) clocks for low power operation. pci_st op# is synchronized by the ICS9148-18 internally. the minimum that the pciclk (0:4) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:4) clocks. pciclk (0:4) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:4) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ICS9148-18 . the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ICS9148-18 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9148. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state.
6 ICS9148-18 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internally by the ICS9148-18 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the power on latency is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals during the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the ics9148. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated.
7 ICS9148-18 absolute maximum ratings supply v oltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unles s otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a operating i dd3.0(66) c l = 0 pf; select @ 66mhz 28 100 ma supply current i dd3.3(100) c l = 0 pf; select @ 100mhz 33 100 power down i dd3.3pd c l = 0 pf 100 150 m a supply current input frequency f i v dd = 3.3 v; all outputs loaded 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cp u-p ci1 v t = 1.5 v; 1.5 3 4 ns 1 guaranteed by design, not 100% tested in production. t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5(66) c l = 0 pf; select @ 66.8 mhz 3 25 ma supply current i dd2.5(100) c l = 0 pf; select @ 100 mhz 4 25 ma power down i dd2.5pd c l = 0 pf 100 m a supply current skew 1 t cpu-pci2 v t = 1.5 v; v tl = 1.25 v 1.5 3 4 ns 1 guaranteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters
8 ICS9148-18 electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 w output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 45 w output high voltage v oh2b i oh = -12.0 ma 2 2.3 v output low voltage v ol2b i ol = 12 ma 0.2 0.4 v output high current i oh2b v oh = 1.7 v -41 -19 ma output low current i ol2b v ol = 0.7 v 19 37 ma ris e time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.2 1.6 ns fall time t f2 b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 50 55 % skew t sk2b 1 v t = 1.25 v 65 175 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 140 250 ps jitter, one sigma t j1s2b 1 v t = 1.25 v 30 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 150 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output impedance 1 r dsp5 v o = v dd *(0.5) 20 60 ohm output impedance 1 r dsn5 v o = v dd *(0.5) 20 60 ohm output high voltage v oh5 i oh = -12 ma 2.6 3.1 v output low voltage v ol5 i ol = 9 ma 0.17 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 16 42 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.9 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.8 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production.
9 ICS9148-18 electrical characteristics - pciclk t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output impedance 1 r dsp1 v o = v dd *(0.5) 12 55 w output impedance 1 r dsn1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -11 ma 2.6 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.1 0.4 v output high current i oh1 v oh = 2.0 v -62 -22 ma output low current i ol1 v ol = 0.8 v 16 57 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.1 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 175 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 13 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 120 250 ps 1 guaranteed by design, not 100% tested in production.
10 ICS9148-18 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. 3 optional crystal load capacitors are recommended. capacitor values: c1, c2 : crystal load values determined by user c3 : 100pf ceramic all unmarked capacitors are 0.01f ceramic
11 ICS9148-18 ordering information ics9148f-18 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device t ype (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp symbol common dimensions variations d min. nom. max. n min. nom. max. a 0.068 0.073 0.078 14 0.239 0.244 0.249 a1 0.002 0.005 0.008 16 0.239 0.244 0.249 a2 0.066 0.068 0.070 20 0.278 0.284 0.289 b 0.010 0.012 0.015 24 0.318 0.323 0.328 c 0.004 0.006 0.008 28 0.397 0.402 0.407 d see variations 30 0.397 0.402 0.407 e 0.205 0.209 0.212 e 0.0256 bsc h 0.301 0.307 0.311 l 0.025 0.030 0.037 n see variations 0 4 8 dimensions in inches ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

▲Up To Search▲

Price & Availability of ICS9148-18

	To Download ICS9148-18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .